On-site courses on VHDL/Verilog training programs are tailored to the requirements and needs the individual companies. For all these courses, a reference book is available and lecture material and study guide will be provided. Courses can be scheduled as intensive day-long courses, or they can be spread over several weeks. Several course descriptions are listed here.
1. Introductory Logic Design with Verilog (2 Days)
This course discusses logic design concepts using Verilog Hardware Description Language. The course begins with presenting main concepts of Verilog and the use of this language in modeling digital system components. We will then present switch level logic, combinational circuits and sequential circuits. At each stage, we will show Verilog coding schemes for logic components that are discussed. Building gates from CMOS switches, logic minimization methods, programmable logic devices, state machines, counters and functional registers will be discussed and accompanied by Verilog examples. At the end, a system based on basic logic components will be described and coded in Verilog.
2. Verilog Hardware Description Language (3 Days)
This course emphasizes on language concepts of Verilog for design and description of hardware. The language will be presented in a bottom-up fashion. Low level transistor and switch components will be presented first. Structural coding for wiring transistor, gate, or other predefined components will be presented. We will then focus our attention or higher levels of abstraction such as dataflow and behavioral. At the dataflow level Verilog coding for bussing, register constructs, large combinational circuits will be discussed and ways of wiring these components into larger structures will be presented. At the behavioral level, complex systems consisting of control and data units will be discussed. After completing the presentation of the language, synthesis with Verilog will be discussed. We will present individual synthesizable focused modules to cover synthesizable constructs of Verilog. This will be followed by a complete example for synthesis.
3. Top-Down Design with Verilog (1 Day)
This one-day course focuses on top-down design methodologies with use of the Verilog hardware description language. A simple, but general, example will be used. The example will be partitioned into its subcomponents and for all subcomponents Verilog code will be shown. Partitioning continues until the design example is broken into available modules of a predefined library. After the completion of the design-partitioning phase, library components will be wired up in a bottom-up fashion to generate a simulatable Verilog description for the complete design. Role of simulation and synthesis in a design process will be illustrated.
4. Design and Modeling with VHDL (3 Days)
This course emphasizes on language concepts of VHDL for design and description of hardware. The language will be presented in a bottom-up fashion. Low level gate modeling techniques with varying timing details will be presented first. Structural level of abstraction for wiring predefined gate and other predefined components will be presented. We will then focus our attention or higher levels of abstraction such as dataflow and behavioral. At the dataflow level VHDL constructs for various forms of bussing, register constructs, and large combinational circuits will be discussed and ways of wiring these components into larger structures will be presented. At the behavioral level, complex systems consisting of control and data units will be discussed. We will present VHDL modeling of state machines and controllers at the behavioral level. After completing the presentation of the language, using VHDL for synthesis will be discussed. We will present individual architectures focusing on synthesizable constructs of VHDL. This will be followed by a complete example for synthesis.
5. Top-Down Design with VHDL (1 Day)
This one-day course focuses on top-down design methodologies with use of the VHDL hardware description language. A simple, but general, example will be used. The example will be recursively partitioned into its subcomponents and for all subcomponents VHDL corresponding descriptions will be shown. Top-down partitioning continues until the design example is broken into available components of a predefined library. After the completion of the design-partitioning phase, library components will be wired up in a bottom-up fashion to generate a simulatable VHDL description for the complete design. Role of simulation and synthesis in a design process will be illustrated.
6. Computer Architecture with VHDL (3 Days)
This course focuses on design and implementation of CPU structures. We will present a small processor example and show a bussing structure for it. VHDL will be used to describe registers, busses and the controller for this CPU. The goal is to be able to present low level details of computing machines utilizing hardware description methods offered by VHDL. When the design of the CPU has been presented, a VHDL memory model will be presented and a minimum working system will be obtained. This minimum system will be used in a board level design that includes a cache, a DMA and an input/output device. System level details of computer structures will be illustrated in this part. Cache structures, will be presented and described in VHDL. Various cache techniques and their implementation will be discussed. When discussing the DMA, bussing and bus arbitration and system level handshaking will be discussed. For a clear picture of how these parts are implemented and put together, at each stage VHDL models will be used. Topics covered in a college computer architecture course will be covered by presenting corresponding VHDL models.
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