VSC (VHDL to SystemC Converter)

VSC is the ideal tool for design teams needing a reliable flow from synthesizable VHDL RTL descriptions to system level SystemC codes. Using VSC gives designers the ability to use previously designed VHDL components in their C/C++ designs. With VSC, you can design in VHDL and enjoy the power and flexibility that C or C++ provides for testbench design or for system software description. This tool allows designers to integrate components written in C or C++ with VHDL components by translating their VHDL components to SystemC and simulating with C/C++.

 

VSC Advantages

Here are some of the advantages of the VSC VHDL translator:

   - Enables reuse of previously designes VHDL componenets in SystemC
   - Solves co-simualtion problem
   - Accelerates System Level Design process
   - Improves speed and quality of SOC design process
   - Enables designers to use the power of C or C++ for developing complex testbenches for VHDL designs

 

VSC Environment

To fully utilize the VSC translator we have packaged it in our user friendly GUI called ROSTA and have included utility programs for code development, simulation, waveform editing, and testing the translated code.

Translated Code

Translation is easy and the generated SystemC code is easy to incorporate in other designs. Here is a simple example translation. 

 

System Requirements

VSC package runs on Windows 2000 or newer.