TVS (Translation to VHDL/Verilog from SystemC for Synthesis)

SystemC is a powerful language for developing a complete system description. While SystemC is a new high level specification language, VHDL and Verilog are well-known HDLs which are extensively supported by EDA tools. 

A major problem for designers using SystemC (from transaction level down to RTL), as their system-level description language, is the lack of a real synthesis tool for the RT-level SystemC descriptions. Manual handling of this process is a hard and time consuming task, and is prone to errors.

TVS provides a reliable flow from RTL SystemC code to synthesizable HDL descriptions. It carries out this task in a very short time, and decreases time-to-market.  Thus, SystemC design flow can be completely linked to the physical flow in order to take advantage of existing tools such as HDL synthesis tools.

 

TVS Advantages

By automatic translation from SystemC to VHDL/Verilog, we double benefit from system-level description power of SystemC and wide support of HDL back-end tools. Major advantages of TVS are:

      -   Completing SystemC-based system-level design flow
      -   Skipping the tedious manual translation of RTL SystemC descriptions to supported entry formats of commercial synthesis tools
   -   Providing  a  reliable  flow  from SystemC descriptions to synthesizable HDL models
   -   Decreasing time-to-market
   -   Providing  a  way  for  synthesizing  SystemC descriptions, independent of synthesis tools

 

 

TVS Environment

To fully utilize the TVS translator we have packaged it in our user friendly GUI called ROSTA and have included utility programs for code development, simulation, waveform editing, and testing the translated code. 

 

 

Translated Code

Translation is easy and the generated VHDL code is easy to incorporate in other designs.  Here is a simple example translation.

 

System Requirements

TVS package runs on Windows 2000 or newer.