A Scenario of VSC

VSC is a program for translation of RT level HDL models into SystemC. The tool is useful for making the generated SystemC code simulatable along with other SystemC or C++ codes.

A scenario of use is when in a Hardware/Software partitioning process, software in C++ is decided and the HDL model of the CPU to run this software is available. The combination of the HDL model of the CPU and the software in C++, on one side, and partitioned hardware in SystemC, on the other side, form the complete system for simulation.

VSC translation takes the HDL model of the CPU, translates it to SystemC, so that all components of our system can be simulated in SystemC. This scenario provides an easy environment for mixed RT, C++ simulation.