A Scenario of TVS

TVS is a program for translation of RT level SystemC models into synthesizable HDL codes. The tool is useful for synthesizing hardware part of a C++ high level description of a system.

A scenario of use is when in a Hardware/Software partitioning process, software in C++ is decided and the HDL model of the CPU to run this software is available. The combination of the HDL model of the CPU and the software in C++ compiled into binary, on one side, and partitioned hardware in HDL, on the other side, form the complete system for simulation.

In addition to synthesis, TVS translation provides HDL models for a complete system RT level HDL simulation.